Implementing the Rivest, Shamir, Adleman cryptographic algorithm on the Motorola 56300 family of digital signal processors

Abstract

The Rivest, Shamir, Adleman (RSA) algorithm [Rivest et al. 1978] is one of a class of cryptographic algorithms that utilize very large precision arithmetic. Multiplication, division, addition and subtraction typically need to be implemented with 512 or more bits precision-and the need for more precision grows as computational processing speeds increase. Digital signal processors are one natural way to create fast cryptographic systems because they have hardware optimized for fast arithmetic. The 56300 family of DSPs possesses characteristics that are well suited for this type of algorithm. These DSPs operate on 24 bit word sizes, and can do multiply accumulates in one clock cycle. We consider how to effectively apply these properties to obtain a fast implementation of algorithms used for RSA cryptography. The presentation is in three parts. The first section presents the RSA algorithm, with emphasis on the implementation approach use. The second section consists of a brief discussion of some salient architectural features of the 56300 family. Finally, we combine these two to obtain efficient implementations of the critical sections of the RSA algorithm.