Estimating the effect of single-event upsets on microprocessors

Abstract

Evaluating the impact of single-event upsets (SEUs) on complex VLSI circuits in general, and microprocessors in particular, requires an interdisciplinary approach, that includes soft error modeling, accelerated measurements, derating of the raw error rates, and specialized design tools. This paper discusses modeling techniques employed to estimate the soft error rates (SER) of storage cells, provides results of accelerated measurements for three technology nodes, and presents a technique for derating the raw error rates by simulated error injection. We use the measurement results to validate and calibrate the models. Then present the tool employed for deriving the SER of the Advanced Micro Devices processor code-named “Bulldozer” and examples of estimated SER. Our approach enables the cost-effective mitigation of SEU by employing data integrity protection for the most sensitive logic.