An approach for exhaustive self testing of LUTs in an FPGA using Walsh configurations

Abstract

This paper presents a new methodology for achieving an exhaustive testing and diagnosis of one of the main FPGA resources, which is the look-up table (LUT). The proposed methodology utilizes a total of log2(2N+2) Walsh configurations to achieve a 100% fault coverage, including all possible stuck-at and bridging faults for N-input LUTs. The Walsh configurations are derived by using Walsh vectors to construct truth tables for the LUT. A fault compression method has been used in order to test more LUTs in parallel and that is designed in combination of Walsh configurations and with a parallel-in-serial-out (PISO) shift register. This method of fault compression also enables fault diagnosis, where the faulty LUTs can be identified. The proposed methodology was implemented on Spartan series FPGAs via an automated approach utilizing a PC through a parallel port communication. The automation program has been written in PERL and C and by utilising Xilinx tools. It is shown from the test results that total testing time required to exhaustively test 200 LUTs for all possible faults is 7.5 minutes. Moreover this method uses minimal input output blocks (IOBs) and provides 100% fault coverage.