{"title":"Avalanche transistor short pulse generator trials for GPR","authors":"Aitykul Omurzakov, A. K. Keskin, A. S. Turk","doi":"10.1109/UWBUSIS.2016.7724188","DOIUrl":null,"url":null,"abstract":"This paper presents impulse generator for ground penetrating radar (GPR) transmitter based on multiplication effect of avalanche transistor. Different impulse generators are designed using single and multiple avalanche transistors. Circuits with multiple transistors used both serial and parallel connections of transistors. 100 kHz signal with 2.2 V and 3 ns pulse width was used as a trigger signal. 280 V DC bias voltage required for single and triple cascaded transistor circuit. Bias voltage for double and quadruple transistor circuit was 370 V DC. Maximum 150 V output with 1.5 ns pulse width was obtained. Circuit schematics and results are demonstrated.","PeriodicalId":423697,"journal":{"name":"2016 8th International Conference on Ultrawideband and Ultrashort Impulse Signals (UWBUSIS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 8th International Conference on Ultrawideband and Ultrashort Impulse Signals (UWBUSIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/UWBUSIS.2016.7724188","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper presents impulse generator for ground penetrating radar (GPR) transmitter based on multiplication effect of avalanche transistor. Different impulse generators are designed using single and multiple avalanche transistors. Circuits with multiple transistors used both serial and parallel connections of transistors. 100 kHz signal with 2.2 V and 3 ns pulse width was used as a trigger signal. 280 V DC bias voltage required for single and triple cascaded transistor circuit. Bias voltage for double and quadruple transistor circuit was 370 V DC. Maximum 150 V output with 1.5 ns pulse width was obtained. Circuit schematics and results are demonstrated.