Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems Pub Date : 2009-10-07 DOI:10.1109/DFT.2009.33

Joon-Sung Yang, B. Nadeau-Dostie, N. Touba

引用次数: 8

Abstract

Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving the control points. This paper investigates methods to further reduce the area overhead by replacing dedicated flip-flops which could not be replaced in [Yang 09]. A new algorithm (alternative selection algorithm) is proposed to find candidate flip-flops out of the fan-in cone of a test point. Experimental results indicate that most of the not-replaced flip-flops in [Yang 09] can be replaced and hence even more significant area reduction can be achieved with minimizing the loss of testability.

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通过更多地使用功能触发器来驱动控制点，减少BIST的测试点面积

最近，[Yang 09]提出了一种新的伪随机内置自检(pseudo-random built-in self-test, BIST)测试点插入方法，该方法尝试使用功能触发器驱动控制测试点，而不是额外增加专用触发器驱动控制点。本文研究了通过替换在[Yang 09]中无法替换的专用触发器来进一步减少面积开销的方法。提出了一种从测试点的扇入锥中寻找候选触发器的新算法(备选选择算法)。实验结果表明，[Yang 09]中大多数不可替换的人字拖都是可以替换的，因此可以在最小化可测试性损失的情况下实现更显着的面积减少。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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