Design of Miniaturized On-chip SIW Cavity Filter and Diplexer in 65nm CMOS Process

Abstract

A miniaturized on-chip substrate integrated waveguide (SIW) bandpass filter (BPF) and diplexer are designed in a 65nm CMOS process. The miniaturization of 42% is achieved by carving slots in the top layer of the SIW cavity. The designed two pole bandpass filter has a simulated 3 dB bandwidth of 11.1% around 70 GHz, while the diplexer has 3-dB bandwidths of 15.3% GHz and 14.86% around 71 and 90.9 GHz, respectively. Moreover, the isolation between two output ports of the diplexer is greater than -27.3 dB.