Formalization of PLC programs to sustain reliability

M. Younis, Georg Frey
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引用次数: 22

Abstract

The complexity of existing PLC programs precludes dealing with or modifying them. The interest in the formalization of PLC programs has increased in recent years to overcome this problem. Formal methods can provide for the development of PLC programs, since they serve as a medium to analyze and verify them due to increased awareness of safety and quality. This is done by performing what is known as verification and validation (V&V). Moreover formal methods support reuse of already implemented PLC programs to meet new production demands. This paper examines different possibilities to formalize PLC programs. It explains the pros and cons of these different alternatives. The paper outlines a formal description of timers and counters used in PLC programs according to the alternative that fulfills the criteria best.
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PLC程序的形式化以保持可靠性
现有PLC程序的复杂性使其无法处理或修改。近年来,为了克服这个问题,人们对PLC程序的形式化越来越感兴趣。正式的方法可以提供PLC程序的开发,因为它们作为分析和验证它们的媒介,因为提高了安全和质量意识。这是通过执行所谓的验证和确认(V&V)来完成的。此外,正式的方法支持重用已经实现的PLC程序,以满足新的生产需求。本文探讨了形式化PLC程序的不同可能性。它解释了这些不同选择的优点和缺点。根据最符合标准的备选方案,概述了PLC程序中使用的定时器和计数器的正式描述。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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