A 12-bit digital-to-time converter (DTC) for time-to-digital converter (TDC) and other time domain signal processing applications

Abstract

This paper describes a digital-to-time converter (DTC) architecture that can be used as a fine interpolator in a time-to-digital converter (TDC) or as an adjustable delay in clock deskewing, for example. The new architecture of the DTC achieves adjustable sub-ps-level resolution with high linearity in ns-level dynamic range. The propagation delay adjustment is implemented by digitally controlling both the unit load capacitors and the discharge current of the load capacitance. The proposed DTC achieves 610 fs resolution and ∼1.25 ns dynamic range. The total simulated power consumption is 3.5 mW with 125 MHz input signal frequency with 3 V supply. The design was simulated using a 0.35 µm CMOS process.