Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Abstract

Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the VD-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible VTH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.