{"title":"VLSI architecture of a MPEG-4 visual renderer","authors":"Quynh-Lien Nguyen-Phuc, C.M. Sorolla","doi":"10.1109/SIPS.2001.957358","DOIUrl":null,"url":null,"abstract":"This paper presents the architecture of a hardware block supporting the real-time rendering of all 2D natural or synthetic visual objects proposed by the MPEG-4 standard as well as sprite decoding. It is compliant to main profile, Level3 and hybrid visual profile. A software model allows us to validate the visual quality of the rendered scene. The complexity of this architecture is evaluated and the architectural choices are validated by means of simulations of a behavioral model.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2001.957358","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper presents the architecture of a hardware block supporting the real-time rendering of all 2D natural or synthetic visual objects proposed by the MPEG-4 standard as well as sprite decoding. It is compliant to main profile, Level3 and hybrid visual profile. A software model allows us to validate the visual quality of the rendered scene. The complexity of this architecture is evaluated and the architectural choices are validated by means of simulations of a behavioral model.
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