Low power high speed switched current comparators for current mode ADC

Abstract

Two topologies of SI comparator for low power current mode circuit implementation are presented. Employing different input stages, these two comparators are suitable to different application cases. Controlled by two complementary clock signals, the proposed comparator operates in a master and slave manner. Sharing a 0-static-power-dissipated dynamic latched comparator as the output comparators, both high power efficiency and high speed are acquired for these two comparators. Designed and simulated in TSMC 0.18 mum mixed signal CMOS technology with 1.8 V supply voltage, the proposed SI comparators achieve a current sensitivity up to 0.2 muA, and a sampling frequency up to 1 GHz, with 8.6 bits resolutions.