{"title":"Current Reuse Oscillator Design for 5G Mobile Application using 90nm CMOS","authors":"K.A. Karthigeyan, S. Radha","doi":"10.1109/ICCSP48568.2020.9182135","DOIUrl":null,"url":null,"abstract":"This paper presents a current reuse oscillator designed for 5G millimeter band frequencies. The designed was VCO simulated with low-Q inductor on-chip CMOS integration. The oscillator generates a signal of 440mV amplitude running at 27. 7S GHz with the phase noise of -102.5dBc and 550 mV amplitude running at 40 GHz with the phase noise of-103.6 dBc at lMHz carrier offset. The oscillator circuit designed from a 1V supply drawing bias currents of 1.5 mA and 1 mA DC current for the lowest and highest frequency band operation.","PeriodicalId":321133,"journal":{"name":"2020 International Conference on Communication and Signal Processing (ICCSP)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Communication and Signal Processing (ICCSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSP48568.2020.9182135","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents a current reuse oscillator designed for 5G millimeter band frequencies. The designed was VCO simulated with low-Q inductor on-chip CMOS integration. The oscillator generates a signal of 440mV amplitude running at 27. 7S GHz with the phase noise of -102.5dBc and 550 mV amplitude running at 40 GHz with the phase noise of-103.6 dBc at lMHz carrier offset. The oscillator circuit designed from a 1V supply drawing bias currents of 1.5 mA and 1 mA DC current for the lowest and highest frequency band operation.