{"title":"Tera-scale computing and interconnect challenges - 3D stacking considerations","authors":"J. Bautista","doi":"10.1109/HOTCHIPS.2008.7476514","DOIUrl":null,"url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Hot Chips 20 Symposium (HCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HOTCHIPS.2008.7476514","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
