Pub Date : 2008-08-01DOI: 10.1109/HOTCHIPS.2008.7476538
S. Sheng, A. Abo, P. Chi, R. Contreras, R. Gupta, H. Huang, L. Lynn, E. Macdonald, K. Nam, R. Narayanaswami, S. Stoiber, E. Su, D. Yee
Presents a collection of slides covering the following: single-chip NTSC/PAL television; mobile applications; analog television; terrestrial TV; analog TV signaling; TV architecture; direct conversion TV-on-a-chip; NTSC/ PAL receiver; low-noise amplifier; mixer; LO harmonics; harmonic rejection filtering; harmonic rejection mixing; LO generation; VSB Nyquist filtering; and digital TV.
{"title":"A 300-mW single-chip NTSC/ PAL television for mobile applications","authors":"S. Sheng, A. Abo, P. Chi, R. Contreras, R. Gupta, H. Huang, L. Lynn, E. Macdonald, K. Nam, R. Narayanaswami, S. Stoiber, E. Su, D. Yee","doi":"10.1109/HOTCHIPS.2008.7476538","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2008.7476538","url":null,"abstract":"Presents a collection of slides covering the following: single-chip NTSC/PAL television; mobile applications; analog television; terrestrial TV; analog TV signaling; TV architecture; direct conversion TV-on-a-chip; NTSC/ PAL receiver; low-noise amplifier; mixer; LO harmonics; harmonic rejection filtering; harmonic rejection mixing; LO generation; VSB Nyquist filtering; and digital TV.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-08-01DOI: 10.1109/HOTCHIPS.2008.7476531
Samuel Williams, David A. Patterson, L. Oliker, J. Shalf, Kathy Yelick
This article consists of a collection of slides from the authors' conference presentation. The Roofline model is a visually intuitive figure for kernel analysis and optimization. The authors believe undergraduates will find it useful in assessing performance and scalability limitations. It is easily extended to other architectural paradigms. It is easily extendable to other metrics: performance (sort, graphics, crypto...) bandwidth (L2, PCIe, ...). A performance counters could be used to generate a runtime-specific roofline that would greatly aide the optimization.
{"title":"The roofline model: A pedagogical tool for program analysis and optimization","authors":"Samuel Williams, David A. Patterson, L. Oliker, J. Shalf, Kathy Yelick","doi":"10.1109/HOTCHIPS.2008.7476531","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2008.7476531","url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. The Roofline model is a visually intuitive figure for kernel analysis and optimization. The authors believe undergraduates will find it useful in assessing performance and scalability limitations. It is easily extended to other architectural paradigms. It is easily extendable to other metrics: performance (sort, graphics, crypto...) bandwidth (L2, PCIe, ...). A performance counters could be used to generate a runtime-specific roofline that would greatly aide the optimization.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125027905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-08-01DOI: 10.1109/HOTCHIPS.2008.7476518
J. Nickolls
{"title":"Scalable parallel programming with CUDA introduction","authors":"J. Nickolls","doi":"10.1109/HOTCHIPS.2008.7476518","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2008.7476518","url":null,"abstract":"","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123785828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-08-01DOI: 10.1109/HOTCHIPS.2008.7476563
Shailender Chaudhry
This article consists of a collection of slides from the author's conference presentation. Some of the specific areas/topics discussed include: Use of CMT Resources for Single-Thread Performance; and HW Transactional Memory.
{"title":"Rock: A SPARC CMT processor","authors":"Shailender Chaudhry","doi":"10.1109/HOTCHIPS.2008.7476563","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2008.7476563","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Some of the specific areas/topics discussed include: Use of CMT Resources for Single-Thread Performance; and HW Transactional Memory.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-08-01DOI: 10.1109/HOTCHIPS.2008.7476533
S. Thrun
Presents a collection of slides covering the following topics: unmanned ground vehicles; drive-by-wire system; and steering control.
展示了一系列涵盖以下主题的幻灯片:无人驾驶地面车辆;线控系统;以及转向控制。
{"title":"Making cars drive themselves","authors":"S. Thrun","doi":"10.1109/HOTCHIPS.2008.7476533","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2008.7476533","url":null,"abstract":"Presents a collection of slides covering the following topics: unmanned ground vehicles; drive-by-wire system; and steering control.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127697099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-08-01DOI: 10.1109/HOTCHIPS.2008.7476514
J. Bautista
This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.
{"title":"Tera-scale computing and interconnect challenges - 3D stacking considerations","authors":"J. Bautista","doi":"10.1109/HOTCHIPS.2008.7476514","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2008.7476514","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Discusses tera-scale computing and interconnect challenges. Suggests that 3D stacking is an attractive solution for both a large last level cache and increasing bulk DRAM capacities.","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133385984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-08-01DOI: 10.1109/hotchips.2008.7476540
Michael Toksvig, Parthasarathy Sriram, John Matheson, Brian Cabral, Brian Smith
{"title":"NVIDIA Tegra","authors":"Michael Toksvig, Parthasarathy Sriram, John Matheson, Brian Cabral, Brian Smith","doi":"10.1109/hotchips.2008.7476540","DOIUrl":"https://doi.org/10.1109/hotchips.2008.7476540","url":null,"abstract":"","PeriodicalId":134939,"journal":{"name":"2008 IEEE Hot Chips 20 Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124254526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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