Design of low power two bit magnitude comparator using adiabatic logic

Abstract

This paper reports a new design of low power two bit magnitude comparator with adiabatic logic in 0.18µm CMOS technology. The proposed design shows the improvement in power delay product (PDP) of 66.76% to 82.97% with varying power supply for 1.1V to 2.0V as compared to conventional design. PDP of proposed design shows an improvement of 73.98% to 81.15 % with temperature varying from 50°C to 10°C as compared to conventional design. Results show a significant improvement in terms of PDP for proposed design as compared to existing conventional designs.