M. H. Ibrahim, A. Hanifa, S. Pramono, M. E. Sulistyo, I. Iftadi
{"title":"Design and Development of Bit Error Measurement using FPGA for Visible Light Communication","authors":"M. H. Ibrahim, A. Hanifa, S. Pramono, M. E. Sulistyo, I. Iftadi","doi":"10.1109/ISRITI51436.2020.9315411","DOIUrl":null,"url":null,"abstract":"Bit error rate (BER) is a fundamental performance measurement of data transmission and communication link. BER measures. Incorporating with digital baseband processing in transceiver, BER measurement can be integrated in a field programmable gate array (FPGA). A Cyclone IV E EP4CE115 is implemented as BER tester to measure performance of visible light communication (VLC) link. The flexibility of FPGA allows the proposed BER measurement system design to add features such as pseudo random bit sequence (PRBS) generator, burst error generator and delay control for synchronization. It shows that design capable to measure VLC link up to 2 Mbps due to limitation of VLC analog front end (AFE).","PeriodicalId":325920,"journal":{"name":"2020 3rd International Seminar on Research of Information Technology and Intelligent Systems (ISRITI)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 3rd International Seminar on Research of Information Technology and Intelligent Systems (ISRITI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISRITI51436.2020.9315411","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Bit error rate (BER) is a fundamental performance measurement of data transmission and communication link. BER measures. Incorporating with digital baseband processing in transceiver, BER measurement can be integrated in a field programmable gate array (FPGA). A Cyclone IV E EP4CE115 is implemented as BER tester to measure performance of visible light communication (VLC) link. The flexibility of FPGA allows the proposed BER measurement system design to add features such as pseudo random bit sequence (PRBS) generator, burst error generator and delay control for synchronization. It shows that design capable to measure VLC link up to 2 Mbps due to limitation of VLC analog front end (AFE).
误码率是衡量数据传输和通信链路性能的基本指标。方方面面的措施。结合收发器中的数字基带处理,可以将误码率测量集成到现场可编程门阵列(FPGA)中。采用Cyclone IV E EP4CE115作为误码率测试仪,测量可见光通信(VLC)链路的性能。FPGA的灵活性允许所提出的误码率测量系统设计增加诸如伪随机比特序列(PRBS)发生器、突发错误发生器和同步延迟控制等功能。结果表明,由于VLC模拟前端(AFE)的限制,该设计只能测量高达2mbps的VLC链路。