Device Analysis of Vertically Stacked GAA Nanosheet FET at Advanced Technology Node

Abstract

Moore’s law indicates that several technological developments are currently being digested. Since switching from a simple MOSFET built with a single control gate to one with numerous control gates, the device’s controllability has significantly enhanced. In this paper, the device-level simulation of vertically stacked GAA nanosheet FET is performed for which the various geometrical variations are calibrated. This research Paper examines the impact of these geometrical variations on the performance of the device. The most prominent parameters like ION, IOFF, SS, DIBL, switching ratio, and Threshold voltage values are analyzed. For the device to be considered to have better performance ION should be maximum, IOFF should be minimum. Hence to obtain this the thickness of the nanosheet is varied on the scale of 5nm to 9nm and the width is varied from 10nm to 50nm. The device simulation and analysis are performed using the Visual TCAD - 3D Cogenda tool.