Implementing a cache for a high-performance GaAs microprocessor

[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture Pub Date : 1991-04-01 DOI:10.1145/115952.115967

K. Olukotun, T. Mudge, Richard B. Brown

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引用次数: 16

Abstract

In the near future, microprocessor systems with very high clock rates will use multichip module (MCM) pack- aging technology to reduce chip-crossing delays. In this paper we present the results of a study for the design of a 250 MHz Gallium Arsenide (GaAs) microprocessor t,lrat employs h4CM technology to improve performance. The design study for the resulting two-level split cache st.arts with a baseline cache architecture and then ex- amines the following aspects: 1) primary cache size and degree of associativity; 2) primary data-cache write pol- icy; 3) secondary cache size and organization; 4) pri- mary cache fetch size; 5) concurrency between instruc- tion and data accesses. A trace-driven simulator is used to analyze each design's performance. The results show that memory access time and page-size constraints ef- Cectively limit the size of the primary data and instruc- tion caches to 4I

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实现高性能砷化镓微处理器的缓存

在不久的将来，具有非常高时钟速率的微处理器系统将使用多芯片模块(MCM)封装老化技术来减少芯片交叉延迟。在本文中，我们介绍了一种250 MHz砷化镓(GaAs)微处理器的设计研究结果，该微处理器采用h4CM技术来提高性能。设计研究了基于基线缓存架构的两级分割缓存，然后分析了以下几个方面:1)主缓存的大小和关联度;2)主数据缓存写策略;3)二级缓存的大小和组织;4) pri- Mary缓存读取大小;指令和数据访问之间的并发性。跟踪驱动模拟器用于分析每种设计的性能。结果表明，内存访问时间和页面大小约束有效地将主数据和指令缓存的大小限制在4I

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[1991] Proceedings. The 18th Annual International Symposium on Computer Architecture

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