{"title":"Neural network development using VHDL","authors":"J. M. Avery","doi":"10.1109/ASIC.1989.123181","DOIUrl":null,"url":null,"abstract":"A developmental approach for hardware implementations of neural networks is presented. Neural network architectural representations including both behavioral and structural influences are presented using the VHSIC High-Level Description Language (VHDL). VHDL design entities and configurations are applied to neural network algorithm development and simulation. Neural network design interchange formats are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123181","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A developmental approach for hardware implementations of neural networks is presented. Neural network architectural representations including both behavioral and structural influences are presented using the VHSIC High-Level Description Language (VHDL). VHDL design entities and configurations are applied to neural network algorithm development and simulation. Neural network design interchange formats are discussed.<>
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