{"title":"Design of a high-performance brokaw band-gap reference","authors":"Jun Hu, Yongsheng Yin, Honghui Deng","doi":"10.1109/ICASID.2010.5551518","DOIUrl":null,"url":null,"abstract":"A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2010.5551518","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A high-performance CMOS band-gap reference (BGR) is designed in this paper. The proposed circuit employs the current-mode architecture optimized for low supply voltage applications. The key portion of the circuit employs the Brokaw BGR architecture, in which a three-stage operational amplifier is adopted to get high PSRR and only first-order temperature compensation technology is employed to get a low temperature coefficient. The circuit is on the Chartered 0.18 μ m CMOS process under the operating voltage of 1.8V and its simulation results are presented. The simulation results show that the temperature coefficient is 9 ppm/°K over the −40°C to 125°C temperature range and the fluctuation of reference voltage is within 0.067m V when the power voltage changes from 1.44V to 2.16V. In addition, the PSRR is 108.5dB at 10 kHz, and the power consumption is only 0.355mW1
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