Modeling Data Movement in the Memory Hierarchy in HPC Systems

Abstract

Increasing core counts and cache sizes in modern processors are causing data movement across the memory hierarchy to increase. With High Performance Computing (HPC) systems becoming more and more energy constrained, improving energy efficiency is becoming a necessity. Given its significant impact on system energy efficiency, the data movement costs in terms of energy and performance cannot be neglected. Conventional techniques for modeling and analyzing data movement across the memory hierarchy have proven to be inadequate in helping computer architects and system designers to optimize data movement. Our work is a position statement emphasizing the need for more detailed data movement modeling tools that better quantify how data movement across the memory hierarchy during application execution affects energy and performance. The hope is that exposing more detailed characteristics about the data movement would enable designers to optimize applications and architectures for minimizing data movement and in turn reduce energy and perhaps even increase performance.