{"title":"Linearity improvement base on digital foreground calibration algorithm for a ultra high-speed analog-to-digital converter","authors":"RuiTao Zhang, Jinshan Yu, Z. Zhang, Yong-lu Wang, Zhu Can, Yu Zhou","doi":"10.1109/ICASID.2010.5551519","DOIUrl":null,"url":null,"abstract":"In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-fin CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC.","PeriodicalId":391931,"journal":{"name":"2010 International Conference on Anti-Counterfeiting, Security and Identification","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Conference on Anti-Counterfeiting, Security and Identification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASID.2010.5551519","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-fin CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
