Concurrent error detection in FSMs using transition checking technique

Abstract

As a complexity of VLSI ICs increases, the inclusion of concurrent error detection is becoming a major concern. In this paper, we address the problem of concurrent error detection in finite state machines (FSMs). In particular, we propose an efficient technique for partial self-checking FSM design based on on-line monitoring of FSM state transitions. We focus primarily on describing an adopted behavioral error model and analytical analysis of the proposed technique. Results concerning error coverage, obtained for benchmark FSMs, are reported.