Vdd gate biasing RF CMOS amplifier design technique based on the effect of carrier velocity saturation

Abstract

RF CMOS amplifier design technique using the carrier velocity saturation region on the drain current of the MOS transistor aggressively has been proposed. By setting the transistor gate bias to the power supply voltage (Vdd), stable operation against Vdd variations can be achieved with a simple circuit configuration. By using the technique, a 5 GHz amplifier has been designed and fabricated by using 0.18-μm CMOS process technology. The chip has been operated with a gain variation less than 1 dB having a peak gain of 13.5 dB when Vdd has been changed from 1.2 to 2.9 V. Input and output matching variations are 1 dB and 3 dB with minimum values of ™10.2 dB and ™ 11.5 dB respectively.