Switch level random pattern testability analysis

Abstract

Algorithms are described for calculating controllabilities and observabilities at the switch level, primitives being the MOS switches which conduct in a definite direction. The signal flow direction of each transistor can be found using some heuristic rules developed by N.P. Jouppi (1983). The calculation of controllabilities is then a matter of propagating the probabilities, modulated by the probability that each transistor is conducting, into internal nets of the circuit, starting from the primary inputs of the circuit. As the signals fan in or fan out, the usual probability combination rules are used to estimate the new controllability and observability. The procedures used for assigning directions to MOS switches are discussed. The algorithms are implemented in LTIME, a CMOS timing analyzer. The techniques are also applied to dynamic power dissipation analysis, of CMOS circuits and are used in predicting chip-level failure rates due to hot-electron effects.<>