Rectangular dualisation is used to generate rectangular topologies in top-down floorplanning of integrated circuits. The author presents an efficient algorithm that transforms an arbitrary graph, representing a custom integrated circuit into one suitable for rectangular dualisation. The algorithm uses efficient techniques in graph processing, such as planar embedding, and introduces a novel procedure to transform a tree of biconnected subgraphs into a block neighborhood graph that is a path.<>
{"title":"Automatic building of graphs for rectangular dualisation (IC floorplanning)","authors":"M. Jabri","doi":"10.1109/DAC.1988.14832","DOIUrl":"https://doi.org/10.1109/DAC.1988.14832","url":null,"abstract":"Rectangular dualisation is used to generate rectangular topologies in top-down floorplanning of integrated circuits. The author presents an efficient algorithm that transforms an arbitrary graph, representing a custom integrated circuit into one suitable for rectangular dualisation. The algorithm uses efficient techniques in graph processing, such as planar embedding, and introduces a novel procedure to transform a tree of biconnected subgraphs into a block neighborhood graph that is a path.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127225562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present their work in the use of the VHDL (VHSIC Hardware Development Language) environment on three different models of DEC VAX (1, 4, and 5.8 Mips (million instruction per second)). The work included the development of a number of VHDL models and sequences of input stimuli and the gathering of performance data from their execution. Even though the set of benchmarks is not in any way exhaustive, they represent typical applications, making it possible to derive performance models for predicting both time and memory requirements for VHDL modeling and simulation. It is shown that the performances of the VHDL environment on the three computers correlate perfectly with their Mips figures; thus the performance models developed can be normalized to a 1-Mips VAX machine.<>
{"title":"Experience with the VHDL environment","authors":"M. Loughzail, M. Cote, M. Aboulhamid, E. Cerny","doi":"10.1109/DAC.1988.14730","DOIUrl":"https://doi.org/10.1109/DAC.1988.14730","url":null,"abstract":"The authors present their work in the use of the VHDL (VHSIC Hardware Development Language) environment on three different models of DEC VAX (1, 4, and 5.8 Mips (million instruction per second)). The work included the development of a number of VHDL models and sequences of input stimuli and the gathering of performance data from their execution. Even though the set of benchmarks is not in any way exhaustive, they represent typical applications, making it possible to derive performance models for predicting both time and memory requirements for VHDL modeling and simulation. It is shown that the performances of the VHDL environment on the three computers correlate perfectly with their Mips figures; thus the performance models developed can be normalized to a 1-Mips VAX machine.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134040956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design capture system is presented that allows parameterized schematics and code to be intermixed freely to produce annotated net lists. A key feature of the system is its extensibility. It provides a small set of powerful abstractions for design description that can easily be extended by users. The system also allows convenient graphical specification of layout generators, and has been used to produce several large VLSI chips.<>
{"title":"Parameterized schematics (VLSI)","authors":"R. Barth, B. Serlet, P. Sindhu","doi":"10.1109/DAC.1988.14765","DOIUrl":"https://doi.org/10.1109/DAC.1988.14765","url":null,"abstract":"A design capture system is presented that allows parameterized schematics and code to be intermixed freely to produce annotated net lists. A key feature of the system is its extensibility. It provides a small set of powerful abstractions for design description that can easily be extended by users. The system also allows convenient graphical specification of layout generators, and has been used to produce several large VLSI chips.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An approach is described for hardware verification in the context of the authors' recent success in formally verifying the description of an image-processing chip. They demonstrate that their approach, which uses an implementation of an equational approach to theorem proving developed by D. Kapur and P. Narendran (1985), can be a viable alternative to simulation. In particular, they are able to take advantage of the recursive nature of many circuits, such as n-bit adders, and their techniques allow verification of sequential circuits. To the best of their knowledge this is the first time a complex sequential circuit which was not designed with formal verification specifically in mind has been verified. They describe the discovery of several design errors in the circuit description, detected during the verification attempt (the actual verification could only take place once these errors were removed).<>
{"title":"Formal verification of the Sobel image processing chip","authors":"P. Narendran, J. Stillman","doi":"10.1109/DAC.1988.14760","DOIUrl":"https://doi.org/10.1109/DAC.1988.14760","url":null,"abstract":"An approach is described for hardware verification in the context of the authors' recent success in formally verifying the description of an image-processing chip. They demonstrate that their approach, which uses an implementation of an equational approach to theorem proving developed by D. Kapur and P. Narendran (1985), can be a viable alternative to simulation. In particular, they are able to take advantage of the recursive nature of many circuits, such as n-bit adders, and their techniques allow verification of sequential circuits. To the best of their knowledge this is the first time a complex sequential circuit which was not designed with formal verification specifically in mind has been verified. They describe the discovery of several design errors in the circuit description, detected during the verification attempt (the actual verification could only take place once these errors were removed).<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116023575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors describe an accurate and efficient gate-level delay calculator that automatically characterizes and computes the gate delays of MOS circuits. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both the input and output of a gate, and an innovative approach for handling transmission gate circuits. The highly efficient delay characterization is accomplished through a fast timing simulation technique, a theorem that reduces a two-dimensional delay table into a scaled one-dimensional table, and an incremental characterization process. The delay calculator has been used in a production timing analyzer and a production multiple delay simulator since 1986. The multiple delay simulator performs 5000 times faster than a SPICE-like circuit simulator at only 15% cost of accuracy. Gate delay models, delay characterization, and practical examples are presented.<>
{"title":"An accurate and efficient gate level delay calculator for MOS circuits","authors":"Foong-Charn Chang, Chin-Fu Chen, P. Subramaniam","doi":"10.1109/DAC.1988.14771","DOIUrl":"https://doi.org/10.1109/DAC.1988.14771","url":null,"abstract":"The authors describe an accurate and efficient gate-level delay calculator that automatically characterizes and computes the gate delays of MOS circuits. The high accuracy is attributed to a sophisticated delay model, which includes an accurate representation of the waveform, a consistent and meaningful definition of delay, a consideration of waveform slope effects at both the input and output of a gate, and an innovative approach for handling transmission gate circuits. The highly efficient delay characterization is accomplished through a fast timing simulation technique, a theorem that reduces a two-dimensional delay table into a scaled one-dimensional table, and an incremental characterization process. The delay calculator has been used in a production timing analyzer and a production multiple delay simulator since 1986. The multiple delay simulator performs 5000 times faster than a SPICE-like circuit simulator at only 15% cost of accuracy. Gate delay models, delay characterization, and practical examples are presented.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116869967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. They form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. They then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results of this two-stage simulated annealing have been superior to those with a conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, the authors report a factor-of-two-to-three speed-up in CPU time, together with a 6-to-17% improvement in the estimated wire length.<>
{"title":"Clustering based simulated annealing for standard cell placement","authors":"S. Mallela, Lov K. Grover","doi":"10.1109/DAC.1988.14776","DOIUrl":"https://doi.org/10.1109/DAC.1988.14776","url":null,"abstract":"The authors present a novel technique for reducing the effective problem size for simulated annealing without compromising the solution quality. They form clusters of cells based on their interconnections, and place them first using conventional simulated annealing. They then break up the clusters, and place the individual cells using another simulated annealing process that does a refinement on the placement. The original problem is thus divided into two subproblems, each requiring much less time. The results of this two-stage simulated annealing have been superior to those with a conventional simulated annealing implementation, with more significant improvements observed for larger chips. For chips with more than 2500 cells, the authors report a factor-of-two-to-three speed-up in CPU time, together with a 6-to-17% improvement in the estimated wire length.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117077419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Lathrop, R. Hall, G. Duffy, K. Alexander, R. Kirk
FUNSTRUX has been extended to extract behavioral-level models for a commercial simulator directly from a circuit netlist. Recent advances include a retargetable code generation mechanism, an object-oriented control structure, handling of initialization values, and improved run-time and space requirements of the abstraction process. The authors discuss some of the issues that arise in translating from Lisp to C and from one functional paradigm to another.<>
{"title":"Advances in functional abstraction from structure","authors":"R. Lathrop, R. Hall, G. Duffy, K. Alexander, R. Kirk","doi":"10.1109/DAC.1988.14847","DOIUrl":"https://doi.org/10.1109/DAC.1988.14847","url":null,"abstract":"FUNSTRUX has been extended to extract behavioral-level models for a commercial simulator directly from a circuit netlist. Recent advances include a retargetable code generation mechanism, an object-oriented control structure, handling of initialization values, and improved run-time and space requirements of the abstraction process. The authors discuss some of the issues that arise in translating from Lisp to C and from one functional paradigm to another.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128334398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A methodology is presented for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic.<>
{"title":"An empirical study of on-chip parallelism","authors":"M. L. Bailey, L. Snyder","doi":"10.1109/DAC.1988.14752","DOIUrl":"https://doi.org/10.1109/DAC.1988.14752","url":null,"abstract":"A methodology is presented for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126803637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present an efficient dynamic algorithm for routing replaced gate array macrocells. A novel data structure based on corner stitching is introduced to represent the routing environment in a general gate array, where a uniform grid cannot be superimposed on the basic-cell. The near-optimal routing is accomplished in iterations with an initial shortest-path routing followed by conflict resolution using a coloring procedure and net reordering.<>
{"title":"Routing algorithm for gate array macro cells","authors":"Atreyi Chakraverti, M. Chung","doi":"10.1109/DAC.1988.14837","DOIUrl":"https://doi.org/10.1109/DAC.1988.14837","url":null,"abstract":"The authors present an efficient dynamic algorithm for routing replaced gate array macrocells. A novel data structure based on corner stitching is introduced to represent the routing environment in a general gate array, where a uniform grid cannot be superimposed on the basic-cell. The near-optimal routing is accomplished in iterations with an initial shortest-path routing followed by conflict resolution using a coloring procedure and net reordering.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126899337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel method is presented for verifying functionality in the design of VLSI circuits. The method fits naturally in a methodology based on a hardware description language (HDL). Two programs describe the system under design: (1) its specification and (2) the extracted behavior from its layout. Verifying the design comes down to proving that these programs are correct and equivalent with regard to the HDL semantics. The authors define a process named formal analysis that permits to prove these properties without setting values to the programs inputs. Formal analysis is based on a canonical form of Boolean logic that is named typed Shannon's canonical form. They implemented this method in PRIAM, an efficient circuit prover now used by industrial CPU designers.<>
{"title":"Proving circuit correctness using formal comparison between expected and extracted behaviour","authors":"J. Madre, J. Billon","doi":"10.1109/DAC.1988.14759","DOIUrl":"https://doi.org/10.1109/DAC.1988.14759","url":null,"abstract":"A novel method is presented for verifying functionality in the design of VLSI circuits. The method fits naturally in a methodology based on a hardware description language (HDL). Two programs describe the system under design: (1) its specification and (2) the extracted behavior from its layout. Verifying the design comes down to proving that these programs are correct and equivalent with regard to the HDL semantics. The authors define a process named formal analysis that permits to prove these properties without setting values to the programs inputs. Formal analysis is based on a canonical form of Boolean logic that is named typed Shannon's canonical form. They implemented this method in PRIAM, an efficient circuit prover now used by industrial CPU designers.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126921850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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