Electrical Diagnosis of 7 Series FPGAs Read Sequence Dependent Bram Failure Using Pattern Analysis

Abstract

The BRAM block is a configurable memory module that attaches to a variety of BRAM interface controller. BRAM serves as a relatively large memory structure (i.e. larger than distributed RAMs or a bunch of D-flip-flop grouped together, but much smaller than off chip memory resources). In addition, multiple blocks can be cascaded to create still larger memory. The failure configuration type of BRAM in read operation was screened out by automatic test equipment (ATE). The failure pattern was created in Vivado which integrated logic analyzer (ILA) was inserted to monitor the failure BRAM data and compared against good BRAM data. The successful fault isolation of BRAM failure was mainly relied on pattern analysis as well as BRAM configuration.