A 10-Gb/s equalizer with digital adaptation

Abstract

An equalizer using a digital adaptive algorithm is proposed to minimize hardware cost. The proposed algorithm uses two analog reference levels to detect the low-frequency and high-frequency components of the input amplitude, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply.