Theoretical and practical minimum of the power Consumption of 3 ADCs in SC technique

B. Bechen, T. Boom, D. Weiler, B. Hosticka
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引用次数: 17

Abstract

In this paper the theoretical and practical minimum of the power consumption is investigated for 3 ADC architectures, which are predestined for low conversion speed and applications in low-power sensor readout circuits. The analysis is made for the switched capacitor versions of the SAR ADC, cyclic ADC and sigma-delta modulator. The theoretical limit of the power efficiency is investigated by a commonly used figure of merit (FOM). As a case study two low-power ADCs were designed and fabricated. In order to compare ADCs fabricated in different technologies a technology-independent FOM is introduced.
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SC技术中3个adc的理论和实际最小功耗
本文研究了三种ADC架构的理论和实际最小功耗,这三种架构在低转换速度和低功耗传感器读出电路中的应用是预定的。分析了SAR ADC、循环ADC和σ - δ调制器的开关电容版本。用一种常用的优值图(FOM)研究了功率效率的理论极限。作为实例,设计并制作了两个低功耗模数转换器。为了比较不同工艺制作的adc,介绍了一种与工艺无关的FOM。
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