Efficient hierarchical approach to test generation for digital systems

Abstract

A new hierarchical approach to test generation for digital systems is proposed. Three levels of modeling are exploited: high-level Decision Diagrams (DD) for module test planning and system constraints generation, low-level Boolean differential equations for fault constraints generation, and medium-level Binary DDs for local test pattern generation for modules under the derived set of constraints. The proposed method of generating fault constraints the first time allows us to handle faults which increase the number of states in sequential circuits. Combining the high-level efficiency of solving complex deterministic search problems and medium-level accuracy of fault "transportation" analysis with low-level exact fault activation allows us to reach high efficiency in test generation, and high test quality on the other hand. Experimental results compared to the known test generators are provided for demonstrating the high efficiency of test generation achieved by the proposed approach.