Precise Cache Timing Analysis via Symbolic Execution

D. Chu, J. Jaffar, Rasool Maghareh
{"title":"Precise Cache Timing Analysis via Symbolic Execution","authors":"D. Chu, J. Jaffar, Rasool Maghareh","doi":"10.1109/RTAS.2016.7461358","DOIUrl":null,"url":null,"abstract":"We present a framework for WCET analysis of programs with emphasis on cache micro-architecture. Such an analysis is challenging primarily because of the timing model of a dynamic nature, that is, the timing of a basic block is heavily dependent on the context in which it is executed. At its core, our algorithm is based on symbolic execution, and an analysis is obtained by locating the \"longest\" symbolic execution path. Clearly a challenge is the intractable number of paths in the symbolic execution tree. Traditionally this challenge is met by performing some form of abstraction in the path generation process but this leads to a loss of path-sensitivity and thus precision in the analysis. The key feature of our algorithm is the ability for reuse. This is critical for maintaining a high-level of path-sensitivity, which in turn produces significantly increased accuracy. In other words, reuse allows scalability in path-sensitive exploration. Finally, we present an experimental evaluation on well known benchmarks in order to show two things: that systematic path-sensitivity in fact brings significant accuracy gains, and that the algorithm still scales well.","PeriodicalId":338179,"journal":{"name":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTAS.2016.7461358","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 25

Abstract

We present a framework for WCET analysis of programs with emphasis on cache micro-architecture. Such an analysis is challenging primarily because of the timing model of a dynamic nature, that is, the timing of a basic block is heavily dependent on the context in which it is executed. At its core, our algorithm is based on symbolic execution, and an analysis is obtained by locating the "longest" symbolic execution path. Clearly a challenge is the intractable number of paths in the symbolic execution tree. Traditionally this challenge is met by performing some form of abstraction in the path generation process but this leads to a loss of path-sensitivity and thus precision in the analysis. The key feature of our algorithm is the ability for reuse. This is critical for maintaining a high-level of path-sensitivity, which in turn produces significantly increased accuracy. In other words, reuse allows scalability in path-sensitive exploration. Finally, we present an experimental evaluation on well known benchmarks in order to show two things: that systematic path-sensitivity in fact brings significant accuracy gains, and that the algorithm still scales well.
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
通过符号执行的精确缓存计时分析
我们提出了一个程序的WCET分析框架,重点是缓存微体系结构。这样的分析之所以具有挑战性,主要是因为动态性质的计时模型,也就是说,基本块的计时严重依赖于执行它的上下文。该算法的核心是基于符号执行,并通过定位“最长”符号执行路径来进行分析。显然,一个挑战是符号执行树中难以处理的路径数量。传统上,这一挑战是通过在路径生成过程中执行某种形式的抽象来解决的,但这会导致路径敏感性的丧失,从而导致分析的精度降低。该算法的关键特征是可重用性。这对于保持高水平的路径灵敏度至关重要,从而显著提高准确性。换句话说,重用允许在路径敏感的探索中进行可伸缩性。最后,我们在众所周知的基准上进行了实验评估,以显示两件事:系统路径敏感性实际上带来了显着的准确性提高,并且该算法仍然具有良好的可扩展性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Trading Cores for Memory Bandwidth in Real-Time Systems A Kernel for Energy-Neutral Real-Time Systems with Mixed Criticalities Poster Abstract: Scheduling Multi-Threaded Tasks to Reduce Intra-Task Cache Contention Demo Abstract: Predictable SoC Architecture Based on COTS Multi-Core TaskShuffler: A Schedule Randomization Protocol for Obfuscation against Timing Inference Attacks in Real-Time Systems
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1