A Clock Synchronization Method Based on An Optimized DPLL Equivalent to A Steady State Kalman Filter

Abstract

Precise clock synchronization is indispensable in many scientific and industrial applications, such as timing laboratories, global satellite navigation systems, and distributed collaborative systems, etc. Digital locked loop (DPLL) is an efficient method to realize real-time and precise clock synchronization. One of the problems when the DPLL is used is to select its coefficients for minimum synchronization errors. This paper proposes an optimized DPLL synchronization method which is equivalent to a steady-state Kalman filter. The coefficients of the DPLL are decided by the gain of the Kalman filter. Simulation shows that the proposed method approaches the minimum synchronization error by comparing to the classical DPLL with different bandwidth. The proposed method has less computation demand, but achieves the same synchronization precision as the Kalman filter.