{"title":"Strategies in SIMD Computing for Complex Neural Bioinspired Applications","authors":"J. Madrenas, J. Moreno","doi":"10.1109/AHS.2009.31","DOIUrl":null,"url":null,"abstract":"The scalable architecture of a multiprocessor intended to efficiently accelerate the emulation of large-scale complex systems, in particular massively-parallel bioinspired neural networks, is introduced in this paper. In order to cope with the required processing complexity of a target network size of large number of neurons and synapses, the SIMD configuration is adopted. Special flow-control instructions are proposed to support conditional execution. Also, a modified digital AER scheme allows for the compact emulation of interconnects. Due to its programmable characteristics, the architecture is flexible enough to support the emulation of different neural models and other homogeneous parallel applications.","PeriodicalId":318989,"journal":{"name":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 NASA/ESA Conference on Adaptive Hardware and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AHS.2009.31","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
The scalable architecture of a multiprocessor intended to efficiently accelerate the emulation of large-scale complex systems, in particular massively-parallel bioinspired neural networks, is introduced in this paper. In order to cope with the required processing complexity of a target network size of large number of neurons and synapses, the SIMD configuration is adopted. Special flow-control instructions are proposed to support conditional execution. Also, a modified digital AER scheme allows for the compact emulation of interconnects. Due to its programmable characteristics, the architecture is flexible enough to support the emulation of different neural models and other homogeneous parallel applications.