Bus buffer modeling and optimization for a microprocessor

Abstract

Inserting bus buffer is one significant method for solving the collisions in the microprocessor. And it is pivotal to determine the buffer size because of the performance and hardware resource constraints. This paper proposes a method for estimating the buffer size based on a prioritized M/G/1 queuing model and a high-level simulation model according to a RISC microprocessor. Both the results of queuing network model and the results of simulation model were found to be valuable. With the help of proposed simulation and estimating method, bus buffer size can be determined fast and accurately for the implementation