Ion-Implanted Self-Aligned-Gate Quantum-well Heterostructure FETs

Abstract

Low gate leakage and proper nand p-channel FET thresholds are essential for achieving high performance complementary heterostructure FET (C-HFET) circuits El]. MESFETs and MODFETs have limited potential for C-HFET circuits due to the large leakage currents characteristic of Schottky-gate designs. While insulator-gate HFETs, such as MISFETs and SISFETs, exhibit substantially lower gate leakage at cryogenic temperatures, the leakage of these devices is still too large for room temperature C-HFET operation. Furthermore, the FET thresholds of conventional MISFET and SJSFET devices are fixed at non-optimal values.