Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721238
F. E. Najjar, D. Radulescu, Y. Chen, G. Wicks, P. Tasker, L. F. Eastman
{"title":"Characterization Of The AlGaAs/GaAs Tunneling Emitter Bipolar Transistor","authors":"F. E. Najjar, D. Radulescu, Y. Chen, G. Wicks, P. Tasker, L. F. Eastman","doi":"10.1109/CORNEL.1987.721238","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721238","url":null,"abstract":"","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115410231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721248
P. Blakey, T. Linton
1. INTRODUmON The design of nonlinear transit-time microwave and millimeter-wave semiconductor diodes (such as IMPA?T’s) is often based on simple scaling ideas, sometimes assisted by large-signal time-domain computer simulation. It is often found that simple scaling of structures from one frequency to another does not lead to optimum results. In addition, anticipated performance improvements from design changes (e.g. use of different structures, materials, heatsinking, etc.) are often not achieved. Large-signal time-domain simulation can be used to assist the: design of active microwave and millimeter wave diodes. However such simularion prov~des a per unit area characterization of specific diode structures. It yields efficiency data, output power per unit area, and impedance per unit area, but does not, by itself, predict optimum areas and maximum output powers. A-J plane analysis has been developed to overcome the above problems. It is a rapid graphical procedure which provides good physical insight. A-J plane analysis may be used on a stand-alone basis, to permit rapid assessment of the likely effect of proposed design changes (e.g. different structures, different materials, or different heatsinking arrangements). The combination of A-J plane analysis with large-signal time-domain simulation provides a complete CAD capability for design and optimization (of active diodes. The central idea of A-J plane analysis is to establish the limits of allowed combinations of area (A) and DC cumnt density (4. Allowed combinations an: limited by several mechanisms, including: thermal limitations; space-charge-induced field perturbations; and various impedance limitations. Each of these limitations gives rise to a boundary in the A-J plane between allowed and disallowed combinations of area and cimnt density. The location of each boundary line is a function of material, saucture, and frequency. A-J plane diagrams are figures showing all the A-J plane constraints. The area and DC current density combination corresponding to maximum input power, and the factors limiting the input power, are easily established using A-J plane diagrams. The utility of proposed design changes is easily established by constructing a modified A-J plane diagram and seeing whether the new design permits significantly higher input powers. The organization of the paper is as follows. The mapping of individual design constraints on to the A-J plane is described in the next section. Stand-alone interpretation and use of A-J plane diagrams is discussed in section 3. Examples are provided showing how to assess the influence of changes of heatsinking arrangement, structme, and semiconductor material. Complete design procedures using large-signal timedomain computer simulation in conjunction with A-J plane analysis are discussed in section 4.
{"title":"A-J Plane Analysis: A Technique For Active Diode Design","authors":"P. Blakey, T. Linton","doi":"10.1109/CORNEL.1987.721248","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721248","url":null,"abstract":"1. INTRODUmON The design of nonlinear transit-time microwave and millimeter-wave semiconductor diodes (such as IMPA?T’s) is often based on simple scaling ideas, sometimes assisted by large-signal time-domain computer simulation. It is often found that simple scaling of structures from one frequency to another does not lead to optimum results. In addition, anticipated performance improvements from design changes (e.g. use of different structures, materials, heatsinking, etc.) are often not achieved. Large-signal time-domain simulation can be used to assist the: design of active microwave and millimeter wave diodes. However such simularion prov~des a per unit area characterization of specific diode structures. It yields efficiency data, output power per unit area, and impedance per unit area, but does not, by itself, predict optimum areas and maximum output powers. A-J plane analysis has been developed to overcome the above problems. It is a rapid graphical procedure which provides good physical insight. A-J plane analysis may be used on a stand-alone basis, to permit rapid assessment of the likely effect of proposed design changes (e.g. different structures, different materials, or different heatsinking arrangements). The combination of A-J plane analysis with large-signal time-domain simulation provides a complete CAD capability for design and optimization (of active diodes. The central idea of A-J plane analysis is to establish the limits of allowed combinations of area (A) and DC cumnt density (4. Allowed combinations an: limited by several mechanisms, including: thermal limitations; space-charge-induced field perturbations; and various impedance limitations. Each of these limitations gives rise to a boundary in the A-J plane between allowed and disallowed combinations of area and cimnt density. The location of each boundary line is a function of material, saucture, and frequency. A-J plane diagrams are figures showing all the A-J plane constraints. The area and DC current density combination corresponding to maximum input power, and the factors limiting the input power, are easily established using A-J plane diagrams. The utility of proposed design changes is easily established by constructing a modified A-J plane diagram and seeing whether the new design permits significantly higher input powers. The organization of the paper is as follows. The mapping of individual design constraints on to the A-J plane is described in the next section. Stand-alone interpretation and use of A-J plane diagrams is discussed in section 3. Examples are provided showing how to assess the influence of changes of heatsinking arrangement, structme, and semiconductor material. Complete design procedures using large-signal timedomain computer simulation in conjunction with A-J plane analysis are discussed in section 4.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116779227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721235
A. Chin, P. Bhattacharya
A novel n-p-n bipolax avalanche transistor is demonstrated. Controlled avalanche and large current output is achieved by incorporating in the collector junction a few periods of a symmet- ric or asymmetric multi-quantum well in which only electrons predominanttly multiply. The theory of operation, materials growth by molecular beam epitaxy, impact ionization data in the quantum wells and device performance are described. Optical gains as high as 140 are measured in these transistors.
{"title":"A Controlled-Avalanche Superlattice Transistor","authors":"A. Chin, P. Bhattacharya","doi":"10.1109/CORNEL.1987.721235","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721235","url":null,"abstract":"A novel n-p-n bipolax avalanche transistor is demonstrated. Controlled avalanche and large current output is achieved by incorporating in the collector junction a few periods of a symmet- ric or asymmetric multi-quantum well in which only electrons predominanttly multiply. The theory of operation, materials growth by molecular beam epitaxy, impact ionization data in the quantum wells and device performance are described. Optical gains as high as 140 are measured in these transistors.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124181964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721232
F. Smith, A. Calawa, C. Chen, L. Mahoney, M. Manfra, J.C. Huang, F. Spooner
A new buffer layer has been developed that eliminates backgating in GaAs MESFET's and substantially reduces short-channel effects in GaAs MESFET's with 0.27-/spl mu/m-long gates. The new buffer is grown by molecular beam epitaxy at a substrate temperature of 200/spl deg/C using Ga and As/sub 4/ beam fluxes. The buffer is crystalline, highly resistive, optically inactive, and can be overgrown with high quality GaAs. GaAs MESFET's with a gate length of 0.27 /spl mu/m that incorporate the new buffer show improved dc and RF properties in comparison with a similar MESFET with a thin undoped GaAs buffer.
{"title":"New MBE Buffer For Micron And Quarter-Micron Gate GaAs MESFET's","authors":"F. Smith, A. Calawa, C. Chen, L. Mahoney, M. Manfra, J.C. Huang, F. Spooner","doi":"10.1109/CORNEL.1987.721232","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721232","url":null,"abstract":"A new buffer layer has been developed that eliminates backgating in GaAs MESFET's and substantially reduces short-channel effects in GaAs MESFET's with 0.27-/spl mu/m-long gates. The new buffer is grown by molecular beam epitaxy at a substrate temperature of 200/spl deg/C using Ga and As/sub 4/ beam fluxes. The buffer is crystalline, highly resistive, optically inactive, and can be overgrown with high quality GaAs. GaAs MESFET's with a gate length of 0.27 /spl mu/m that incorporate the new buffer show improved dc and RF properties in comparison with a similar MESFET with a thin undoped GaAs buffer.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121504422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721210
R. Jain
{"title":"Electro-Optic Sampling Of High-speed III-V Devices And ICS","authors":"R. Jain","doi":"10.1109/CORNEL.1987.721210","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721210","url":null,"abstract":"","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121550229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721239
C.I. Huang, M. Cheney, M. Paulus, J. Scheihing, J. Crist, M. Sopko, C. Bozada, C. E. Stutz, R.L. Jones, K. Evans
Heterostructure bipolar transistor (HBT) theory and technology have been comprehensively reviewed by Kroemer [ l ] . the structures studied lby many researchers in various laboratories [for example, see Ref 2 and 3 1 . For microwave application, f of 75 GHz have been demonstrated [2]. Common emitter current gain as high as 2000 has also been reported [ 3 ] . One of the possible approaches to achieve higher frequency performance of an HBT is to reduce the base width. To obtain a thin base, Matsumoto et. al. [ 4 ] proposed an AlAs/GaAs heterostructure in a bipolar transistor to obtain an "inversion base" (hence the name inversion-base bipolar transistor (IBT)). In this structure the base is formed by a two dimensional hole gas created via inversion at the heterointerface. The potential advantages of an IBT are the reduced base width and ease of fabrication. Current gains of 17.1 and 5.6 were obtained at 300 K and 77 K respectively [ 4 ] . It was suggested that the increased current gain at 300 K relative to 77 K may be due to the increase of t$e thermally stimulated electrons which go over the AlAs barrier from the n GaAs emitter to the nGaAs collector. which resulted in demonstrating bipolar transistor action with much improved device performance in terms of current gain and density. The AlGaAs/GaAs HBT is one of
Kroemer对异质结构双极晶体管(HBT)的理论和技术进行了全面的综述[1]。许多研究人员在不同的实验室研究了这些结构[例如，参见参考文献2和31]。在微波应用方面，75 GHz的频率已被证实。据报道，共发射极电流增益高达2000。实现HBT更高频率性能的可能方法之一是减小基宽。为了获得薄基底，Matsumoto et al.[4]在双极晶体管中提出了AlAs/GaAs异质结构，以获得“反转基底”(因此称为反转基底双极晶体管(IBT))。在这种结构中，基底是由在异质界面上通过反转产生的二维空穴气体形成的。IBT的潜在优点是减少了基底宽度和易于制造。在300 K和77 K时，电流增益分别为17.1和5.6。结果表明，在300 K时相对于77 K时电流增益的增加可能是由于从nGaAs发射极到nGaAs集电极越过AlAs势垒的热激电子的增加所致。这导致了双极晶体管的作用，在电流增益和密度方面大大提高了器件性能。AlGaAs/GaAs HBT是其中之一
{"title":"A Study Of GaAs Inversion-Base Bipolar Transistor","authors":"C.I. Huang, M. Cheney, M. Paulus, J. Scheihing, J. Crist, M. Sopko, C. Bozada, C. E. Stutz, R.L. Jones, K. Evans","doi":"10.1109/CORNEL.1987.721239","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721239","url":null,"abstract":"Heterostructure bipolar transistor (HBT) theory and technology have been comprehensively reviewed by Kroemer [ l ] . the structures studied lby many researchers in various laboratories [for example, see Ref 2 and 3 1 . For microwave application, f of 75 GHz have been demonstrated [2]. Common emitter current gain as high as 2000 has also been reported [ 3 ] . One of the possible approaches to achieve higher frequency performance of an HBT is to reduce the base width. To obtain a thin base, Matsumoto et. al. [ 4 ] proposed an AlAs/GaAs heterostructure in a bipolar transistor to obtain an \"inversion base\" (hence the name inversion-base bipolar transistor (IBT)). In this structure the base is formed by a two dimensional hole gas created via inversion at the heterointerface. The potential advantages of an IBT are the reduced base width and ease of fabrication. Current gains of 17.1 and 5.6 were obtained at 300 K and 77 K respectively [ 4 ] . It was suggested that the increased current gain at 300 K relative to 77 K may be due to the increase of t$e thermally stimulated electrons which go over the AlAs barrier from the n GaAs emitter to the nGaAs collector. which resulted in demonstrating bipolar transistor action with much improved device performance in terms of current gain and density. The AlGaAs/GaAs HBT is one of","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133877502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721225
A. T. Yuen, S. Long, E. Hu, G. A. Patterson
Recently there has been increased interest in semiconductor-gate heterostructure FETs [l-41, due to their potentially uniform threshold voltages, as well as their high tolerance of process variations. We have demonstrated and compared two processing schemes, the self-aligned ohmic (SAO) process and the self-aligned implant (SAI) process, for the fabrication of se mico nducto r-"i nsu lato r"-se mico nducto r FETs (SISFET) . The SlSFETs were found to have highly uniform threshold voltages with little backg ati ng effect.
最近，由于半导体栅异质结构场效应管具有均匀的阈值电压，以及对工艺变化的高耐受性，人们对半导体栅异质结构场效应管的兴趣越来越大。我们演示并比较了两种加工方案，即自对准欧姆(SAO)工艺和自对准植入(SAI)工艺，用于制造硅微电感r-“i - nsu”-硅微电感r- fet (SISFET)。发现slsfet具有高度均匀的阈值电压，背景效应很小。
{"title":"Self-aligned Ohmic And Self-Aligned Implant GaAs Gate FET With Integrated Diode","authors":"A. T. Yuen, S. Long, E. Hu, G. A. Patterson","doi":"10.1109/CORNEL.1987.721225","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721225","url":null,"abstract":"Recently there has been increased interest in semiconductor-gate heterostructure FETs [l-41, due to their potentially uniform threshold voltages, as well as their high tolerance of process variations. We have demonstrated and compared two processing schemes, the self-aligned ohmic (SAO) process and the self-aligned implant (SAI) process, for the fabrication of se mico nducto r-\"i nsu lato r\"-se mico nducto r FETs (SISFET) . The SlSFETs were found to have highly uniform threshold voltages with little backg ati ng effect.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134614075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721214
L. Nguyen, M. Foisy, P. Tasker, W. Schaff, A. Lepore, L. Eastman
This paper describes the first experimental evidence which suggests that carrier deconfinement, rather than the low 2DEG sheet density, limits the carrier velocity in pseudomorphic Al/sub x/Ga/Sub 1x/As/In/sub 15/Ga/sub 85/ as MODFET's for 0.1/spl les/ x /spl les/ 0.45. We use C-V at 300K and 77K to characterize charge control and dc-and-rf measurements to evaluate device performance. The highest 2DEG densities are obtained for 0.20 /spl les/ x /spl les/ 0.35 while best device performance for 0.10 /spl les/ x /spl les/ 0.30. The maximum effective velocity v/sub eff/ as deduced from S-parameter measuriments, is independent of sheet density but exhibits a dependence on Al mole fraction similar to that of mobility in bulk AlGaAs [1]. An effective velocity of /spl tilde/ 1.5 x 10/sup 7/ cm/s is estimated for 0.10 /spl les/ x /spl les/ 0.30, 1.3 x 10/sup 7/ cm/s for x 0.35, and 0.9 x 10/sup 7/ cm/s for x = 0.45. Our experimental data suggests for the first time that i) the maximum carrier velocity is not limited by low sheet densities and ii) the transport properties ouside the InGaAs channel have a significant impact on device performance due to the lack of carrier confinement.
{"title":"Carrier Deconfinement Limited Velocity In Pseudomorphic AlGaAsiin GaAs Modulation-doped Field Effect Transistors (MODFET's)","authors":"L. Nguyen, M. Foisy, P. Tasker, W. Schaff, A. Lepore, L. Eastman","doi":"10.1109/CORNEL.1987.721214","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721214","url":null,"abstract":"This paper describes the first experimental evidence which suggests that carrier deconfinement, rather than the low 2DEG sheet density, limits the carrier velocity in pseudomorphic Al/sub x/Ga/Sub 1x/As/In/sub 15/Ga/sub 85/ as MODFET's for 0.1/spl les/ x /spl les/ 0.45. We use C-V at 300K and 77K to characterize charge control and dc-and-rf measurements to evaluate device performance. The highest 2DEG densities are obtained for 0.20 /spl les/ x /spl les/ 0.35 while best device performance for 0.10 /spl les/ x /spl les/ 0.30. The maximum effective velocity v/sub eff/ as deduced from S-parameter measuriments, is independent of sheet density but exhibits a dependence on Al mole fraction similar to that of mobility in bulk AlGaAs [1]. An effective velocity of /spl tilde/ 1.5 x 10/sup 7/ cm/s is estimated for 0.10 /spl les/ x /spl les/ 0.30, 1.3 x 10/sup 7/ cm/s for x 0.35, and 0.9 x 10/sup 7/ cm/s for x = 0.45. Our experimental data suggests for the first time that i) the maximum carrier velocity is not limited by low sheet densities and ii) the transport properties ouside the InGaAs channel have a significant impact on device performance due to the lack of carrier confinement.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721220
M. Chen, W. Schaff, P. Tasker, L. Eastman
=aligned GaAs gate enhancement mode SISFETs with the highest intrinsic g, of 350 mS/mm and 440 mS/mm, and I of 270 mA/mm and 450 mA/mm at 300K an8 77K respectively were obtained on 055 pm gate length devices. Electron velocity enhancement effects were seen through transconductance dependence on gate lenght. The effective channel length in this self-aligned structure was found to be defined by SI+ implanted source and drain regions. The extrapolated p at 77K was > 150,000 cm-'/V.sec and contributed to excellent channel conductance shown firough low knee voltage and low channel resistance which is lower than 1/3 of the total S-D on resistance. The near zero built-in V was obtained due to almost symmetric layer structure, good thermal stability of undoped structure and proper RTA control. The I-V distortion at 77K was found to be a pure geometric effect resulting from angled Si + implant and did not occur in non-angled implant due to undoped structure, unlike the I, collapse in MODFET which is caused by traps. The SISFETs show a large charge modulation capability: at Vg = 0.7V, NS 2 1012/cm2, fast turn on characteristics, and high potential in being used in higk speed logic circuits. These features also made SISFET potential in obtaining high frequency microwave performance. Furthermore intrinsic NDR of SISFETs was found by real space transfer through hot electron injection under certain bias conditions and this indicates SISFETs might have potential in other interesting microwave applications which is still under study. I nt rod u ct io n
{"title":"Processing And DC Performance Of Self-Aligned GaAs Gate SISFET","authors":"M. Chen, W. Schaff, P. Tasker, L. Eastman","doi":"10.1109/CORNEL.1987.721220","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721220","url":null,"abstract":"=aligned GaAs gate enhancement mode SISFETs with the highest intrinsic g, of 350 mS/mm and 440 mS/mm, and I of 270 mA/mm and 450 mA/mm at 300K an8 77K respectively were obtained on 055 pm gate length devices. Electron velocity enhancement effects were seen through transconductance dependence on gate lenght. The effective channel length in this self-aligned structure was found to be defined by SI+ implanted source and drain regions. The extrapolated p at 77K was > 150,000 cm-'/V.sec and contributed to excellent channel conductance shown firough low knee voltage and low channel resistance which is lower than 1/3 of the total S-D on resistance. The near zero built-in V was obtained due to almost symmetric layer structure, good thermal stability of undoped structure and proper RTA control. The I-V distortion at 77K was found to be a pure geometric effect resulting from angled Si + implant and did not occur in non-angled implant due to undoped structure, unlike the I, collapse in MODFET which is caused by traps. The SISFETs show a large charge modulation capability: at Vg = 0.7V, NS 2 1012/cm2, fast turn on characteristics, and high potential in being used in higk speed logic circuits. These features also made SISFET potential in obtaining high frequency microwave performance. Furthermore intrinsic NDR of SISFETs was found by real space transfer through hot electron injection under certain bias conditions and this indicates SISFETs might have potential in other interesting microwave applications which is still under study. I nt rod u ct io n","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125601513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-08-10DOI: 10.1109/CORNEL.1987.721218
H. Levy, H. Lee, O.J. Wu, M. Schneider, E. Kohn
Differing requirements sometimes exist for the characteristics of the gate recess in HEMT and MESFET devices. In particular, the requirements of low noise and high power put different constraints on device design. Low noise applications typically require a minimum in the parasitic source and gate resistance with other related considerations being secondary. Power applications, on the other hand, require the minimization in undepleted charge in the channel to achieve maximum breakdown voltage. Device capacitance is an important consideration in both cases.
{"title":"Engineering Of Spike Doped HEMT Characteristics Through Recess Etch Considerations","authors":"H. Levy, H. Lee, O.J. Wu, M. Schneider, E. Kohn","doi":"10.1109/CORNEL.1987.721218","DOIUrl":"https://doi.org/10.1109/CORNEL.1987.721218","url":null,"abstract":"Differing requirements sometimes exist for the characteristics of the gate recess in HEMT and MESFET devices. In particular, the requirements of low noise and high power put different constraints on device design. Low noise applications typically require a minimum in the parasitic source and gate resistance with other related considerations being secondary. Power applications, on the other hand, require the minimization in undepleted charge in the channel to achieve maximum breakdown voltage. Device capacitance is an important consideration in both cases.","PeriodicalId":247498,"journal":{"name":"IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits, 1987. Proceedings.","volume":"312 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-08-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131645418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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