A novel low power 3T inverter

Abstract

Though CMOS logic inverter is widely appreciated because of its negligible static power consumption still sometimes it is deprecated because of the high dynamic power consumption. The high dynamic power consumption is because of the charging and discharging of the load capacitor and also because of the unwanted short-circuits current from Vdd to ground. The proposed three transistor saturated NMOS inverter reduces the short-circuit current and hence reduces the overall power consumption. The proposed inverter reduces the average power consumption by 35% for any input signal of frequency less than or equal to 1 MHz and by 15% for any input signal up to around 10MHz. But the power consumption slowly increases when the input frequency goes beyond 100 MHz. So the proposed inverter can be used in MHz applications to save a good amount of power.