A 3.5ns, 2W, 20mm216Kb ECL bipolar RAM

Abstract

THIS PAPER WILL DESCRIBE a 3.5ns ECL 16Kb bipolar RAM with a power dissipation of 2W, cell size of 4 9 5 ~ 2 and chip size of 20mm2. The most critical requirements for bipolar RAMs are high speed, low power dissipation and small chip size. Two circuit techniques are proposed to meet the foregoing criteria: ( I ) a Schottky barrier diode (SBD) decoder combined with an address buffer and a latch circuit having three-level VBB; ( 2 ) a Darlington word driver having double-stage discharge circuits. The SBD decoder circuit combined with the address buffer and latch circuits is shown in Figure 1. The decoder reduces access time by 20% compared to a conventional multi-emitter decoder, because the parasitic capacitance CDE at the decoder output can be reduced by about 65%. The lower capacitance is due to the small area and small junction capacitance per unit area. Two SBDs have been connected in series to obtain a forward voltage higher than a base-emitter voltage VBE of the transistor QE. This enables the decoder to be completely cut off, insuring a sufficiently high level at the decoder output. To realize even higher speeds at the system level, an on-chip buffer and latch must be combined with the SBD decoder. However, a simple combination of the conventional address buffer and latch using a series gate’ and SBD decoder cannot be used because of transistor (Ql /Q2) saturation under a given supply voltage (-5.2V); Figure 1. To overcome this problem, an address buffer and latch with a threelevel VBB, also shown in Figure 1, is proposed. The latch operation can be performed by the three-level VBB without any loss in speed. Until the clock CLK turns on, the VBB generator offers a VBB in accordance with the previous address input (ADR) levels as shown in Figure 2. That is, the VBB is set to a lower (higher) level than any address input level for high (low) level address input. Therefore, the outputs of the address buffer are held high or low regardless of the following address input changes. When the clock CLK turns on at to, the output of the VBB generator is switched to a standard VBB level for a 10K or lOOK logic family. Thus, the outputs of the address buffers can be changed in accordance with the address inputs. This address information is retained when the CLK turns off again. Figure 3 shows a Darlington word driver using double-stage discharge circuits connected to each of the transistor emitters. Sufficient discharge currents are provided (I1 = 2mA, I2 = 6mA) without a significant voltage drop on the word line. Conventional delayed discharge circuits are also used at the end of the word lines to increase the cell margin. Since both discharge circuits are delay-type, it is possible to maintain a high current after the word line voltage switches to a low level. The driver reduces further the access time by about 15Yc. The increase in power dissipation is negligibly small in spite of the high