Assurance methods for COTS multi-cores in avionics

Abstract

In recent years, the use of multi-core processors in avionics systems has supported the increase in performance and level of integration of safety-critical functions. However, multi-core processors stretch the current hardware and software assurance processes, which are the foundations of safe design process for airworthiness. The main concern with the use of multi-core processors in the aerospace safety-critical domain is their lack of predictability, which makes safety assessment at component level impractical. We propose thereafter a system level approach wherein the need for determinism is considered for each function implemented on the multi-core processor. This paper details the use of a top-down safety method to isolate high-level sources of non-determinism. This isolation substantiates limiting the scope of the complementary and conventional bottom-up safety assessment. Specific attention is paid to interferences through the proposed interference-aware safety analysis that identifies interference paths, analyzes each path for its effect on the required demonstration of determinism, and justifies mitigation strategies. The result is the mitigation of the shortcomings in the current guidance on multi-core processors, using an approach to safe design and safety methods particularly adapted to complex computational systems with high integration levels.