Exceeding test pattern limitation by multi-clock test methodology

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824091

Jang Jin Hwan, Kim Kyung Ho, Kye Bum Suk

引用次数: 0

Abstract

There are some limitations in the ASIC test. The maximum test pattern depth is one of them. A method to reduce the test pattern depth would be very useful. Hence the authors introduce a method to do this and the target ATE is ADVAN.

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通过多时钟测试方法超过测试模式限制

在ASIC测试中有一些限制。最大测试模式深度是其中之一。减少测试模式深度的方法将非常有用。因此，作者介绍了一种实现这一目标的方法，目标ATE为ADVAN。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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