{"title":"A New and Efficient Algorithm for FPGA Routing","authors":"Z. Liu, Zong-guang Yu, Xiaofeng Gu","doi":"10.1109/ICIEA.2007.4318642","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a new and efficient hybrid Routing algorithm for FPGAs by integrating a Boolean satisfiability algorithm with geometric routing algorithm. It takes advantage of the rip-up-reroute capabilities of the conventional geometric routing algorithm and simultaneous net embedding characteristic of Boolean SAT-based FPGA routing. Experiment results show that compared with the corresponding pure geometric routing algorithm, the running time is dramatic reduced.","PeriodicalId":231682,"journal":{"name":"2007 2nd IEEE Conference on Industrial Electronics and Applications","volume":"65 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 2nd IEEE Conference on Industrial Electronics and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIEA.2007.4318642","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this paper, we propose a new and efficient hybrid Routing algorithm for FPGAs by integrating a Boolean satisfiability algorithm with geometric routing algorithm. It takes advantage of the rip-up-reroute capabilities of the conventional geometric routing algorithm and simultaneous net embedding characteristic of Boolean SAT-based FPGA routing. Experiment results show that compared with the corresponding pure geometric routing algorithm, the running time is dramatic reduced.
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