J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska
{"title":"InP DHBT technology and design for 40 Gbit/s full-rate-clock communication circuits","authors":"J. Godin, M. Riet, S. Blayac, P. Berdaguer, V. Dhalluin, F. Alexandre, M. Kahn, A. Pinquier, A. Kasbari, J. Moulu, A. Konczykowska","doi":"10.1109/GAAS.2002.1049063","DOIUrl":null,"url":null,"abstract":"In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.","PeriodicalId":142875,"journal":{"name":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.2002.1049063","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
In this paper, we present our InP DHBT technology with improved performances, yield and uniformity; and some new design tools, both of which have allowed us to achieve 40+ Gbit/s full-rate-clock circuits, such as the D-flip-flop. These circuits have been characterized and packaged.
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