A Study of Architecture Description Languages from a Model-based Perspective

W. Qin, S. Malik
{"title":"A Study of Architecture Description Languages from a Model-based Perspective","authors":"W. Qin, S. Malik","doi":"10.1109/MTV.2005.2","DOIUrl":null,"url":null,"abstract":"Owing to the recent trend of using application-specific instruction-set processors (ASIP), many architecture description languages (ADLs) have been created. They specify architectures or microarchitectures of processors, and automate tasks including circuit implementation, simulation, retargetable compilation and formal verification. This paper first gives an overview of the existing ADLs. This paper argues that for an ADL to be capable of rigorously specifying a processor, it must be based on a solid foundation which we call the architecture model. The existing ADLs feature a wide variety of formal and ad-hoc architecture models which confines the flexibility and analyzability of the ADLs in one way or another. This paper then discusses the operation state machine (OSM) model, the result of our first attempt to create high-level processor models. The model has features balanced flexibility and analyzability for use in architecture space exploration frameworks for ASIPs. This paper also describes the use of the OSM model in the Mescal architecture description language (MADL), an open-source ADL framework that we developed. Lastly, it points out the potential application of formal verification techniques on OSM","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 Sixth International Workshop on Microprocessor Test and Verification","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2005.2","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

Abstract

Owing to the recent trend of using application-specific instruction-set processors (ASIP), many architecture description languages (ADLs) have been created. They specify architectures or microarchitectures of processors, and automate tasks including circuit implementation, simulation, retargetable compilation and formal verification. This paper first gives an overview of the existing ADLs. This paper argues that for an ADL to be capable of rigorously specifying a processor, it must be based on a solid foundation which we call the architecture model. The existing ADLs feature a wide variety of formal and ad-hoc architecture models which confines the flexibility and analyzability of the ADLs in one way or another. This paper then discusses the operation state machine (OSM) model, the result of our first attempt to create high-level processor models. The model has features balanced flexibility and analyzability for use in architecture space exploration frameworks for ASIPs. This paper also describes the use of the OSM model in the Mescal architecture description language (MADL), an open-source ADL framework that we developed. Lastly, it points out the potential application of formal verification techniques on OSM
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
基于模型的体系结构描述语言研究
由于最近使用特定于应用程序的指令集处理器(ASIP)的趋势,已经创建了许多体系结构描述语言(adl)。它们指定处理器的体系结构或微体系结构,并自动执行包括电路实现、仿真、可重目标编译和形式化验证在内的任务。本文首先对现有的adl进行了概述。本文认为,对于能够严格指定处理器的ADL来说,它必须建立在一个坚实的基础之上,我们称之为体系结构模型。现有的adl具有各种各样的正式和特别的体系结构模型,这些模型以某种方式限制了adl的灵活性和可分析性。然后,本文讨论了操作状态机(OSM)模型,这是我们首次尝试创建高级处理器模型的结果。该模型具有平衡灵活性和可分析性的特点,可用于面向asp的架构空间探索框架。本文还描述了OSM模型在Mescal体系结构描述语言(MADL)中的使用,MADL是我们开发的一个开源ADL框架。最后,指出了形式化验证技术在OSM中的潜在应用
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Is IDDQ Test of Microprocessors Feasible? HW/SW Co-Verification of a RISC CPU using Bounded Model Checking Language-driven Validation of Pipelined Processors using Satisfiability Solvers Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors Retiming Verification Using Sequential Equivalence Checking
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1