This paper presents a pre-silicon validation methodology of Intelreg Itaniumreg processor family (IPF) memory ordering for multi-core processors. The validation methodology includes a multi-core simulation environment, a shared memory multiprocessor reference model, memory ordering checkers, and a tightly combined strategy of stimulus and coverage, specifically developed for IPF memory ordering. The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-silicon validation stage
{"title":"Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors","authors":"Soohong P. Kim","doi":"10.1109/MTV.2005.19","DOIUrl":"https://doi.org/10.1109/MTV.2005.19","url":null,"abstract":"This paper presents a pre-silicon validation methodology of Intelreg Itaniumreg processor family (IPF) memory ordering for multi-core processors. The validation methodology includes a multi-core simulation environment, a shared memory multiprocessor reference model, memory ordering checkers, and a tightly combined strategy of stimulus and coverage, specifically developed for IPF memory ordering. The latest result showed that memory ordering specific focused tests and pseudo-random exercisers were very effective in finding memory ordering bugs in the pre-silicon validation stage","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. D. Guglielmo, F. Fummi, C. Marconcini, G. Pravadelli
This paper presents a functional ATPG framework which exploits the extended finite state machine (EFSM) model to pseudo-deterministically generate test sequences. A constraint solver or a SAT-solver is used to generate test vectors that allow us to uniformly traverse the state space of the design under test (DUT). This definitely increases the ability of the ATPG to observe and control hard-to-detect faults
{"title":"A Pseudo-Deterministic Functional ATPG based on EFSM Traversing","authors":"G. D. Guglielmo, F. Fummi, C. Marconcini, G. Pravadelli","doi":"10.1109/MTV.2005.1","DOIUrl":"https://doi.org/10.1109/MTV.2005.1","url":null,"abstract":"This paper presents a functional ATPG framework which exploits the extended finite state machine (EFSM) model to pseudo-deterministically generate test sequences. A constraint solver or a SAT-solver is used to generate test vectors that allow us to uniformly traverse the state space of the design under test (DUT). This definitely increases the ability of the ATPG to observe and control hard-to-detect faults","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128930065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to increasing demand for faster computations, deeply pipelined processor architectures are being employed to meet desired system performance. Functional validation of such pipelined processors is one of the most complex and expensive tasks in the current systems-on-chip design methodology. While language-based validation techniques have proposed several promising ideas, many challenges remain in applying them to realistic pipelined processors. This paper describes two practical challenges in this methodology: test generation and equivalence checking. The time and resources required for test generation using the existing approaches can be extremely large for today's pipelined processors. Similarly, traditional equivalence checkers are not useful in the context of language-driven model generation and functional validation. This paper outlines our plan to address these challenges using satisfiability checking
{"title":"Language-driven Validation of Pipelined Processors using Satisfiability Solvers","authors":"P. Mishra, Heon-Mo Koo, Zhuo Huang","doi":"10.1109/MTV.2005.14","DOIUrl":"https://doi.org/10.1109/MTV.2005.14","url":null,"abstract":"Due to increasing demand for faster computations, deeply pipelined processor architectures are being employed to meet desired system performance. Functional validation of such pipelined processors is one of the most complex and expensive tasks in the current systems-on-chip design methodology. While language-based validation techniques have proposed several promising ideas, many challenges remain in applying them to realistic pipelined processors. This paper describes two practical challenges in this methodology: test generation and equivalence checking. The time and resources required for test generation using the existing approaches can be extremely large for today's pipelined processors. Similarly, traditional equivalence checkers are not useful in the context of language-driven model generation and functional validation. This paper outlines our plan to address these challenges using satisfiability checking","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121249890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ability to enhance single-thread performance, such as by increasing clock frequency, is reaching a point of diminishing returns: power is becoming a dominating factor and limiting scalability. Adding additional cores is a scalable way to increase performance, but it requires that system designers have a method for developing multithreaded applications. Plasma, (parallel language for system modeling and analysis) is a parallel language for system modeling and multi-threaded application development implemented as a superset of C++. The language extensions are based upon those found in Occam, which is based upon CSP (communicating sequential processes) by C. A. R. Hoare. The goal of the Plasma project is to investigate whether a language with the appropriate constructs might be used to ease the task of developing highly multi-threaded software. In addition, through the inclusion of a discrete event simulation API, we seek to simplify the task of system modeling and increase productivity through clearer representation and increased compile-time checking of the more difficult-to-get-right aspects of systems models (the concurrency). The result is a single language which allows users to develop a parallel application and then to model it within the context of a system, allowing for hardware-software partitioning and various other early tradeoff analyses. We believe that this language offers a simpler and more concise syntax than other offerings and can be targeted at a large range of potential architectures, including heterogeneous systems and those without shared memory
增强单线程性能的能力(例如通过增加时钟频率)正在达到收益递减的程度:功率正在成为一个主要因素，并限制了可伸缩性。添加额外的内核是提高性能的一种可伸缩方式，但它要求系统设计人员有一种开发多线程应用程序的方法。Plasma(用于系统建模和分析的并行语言)是一种用于系统建模和多线程应用程序开发的并行语言，实现为c++的超集。语言扩展基于Occam中的扩展，Occam基于C. A. R. Hoare的CSP(通信顺序进程)。Plasma项目的目标是研究是否可以使用具有适当结构的语言来简化开发高度多线程软件的任务。此外，通过包含离散事件模拟API，我们寻求简化系统建模的任务，并通过更清晰的表示和增加对系统模型中更难以获得的方面(并发性)的编译时检查来提高生产力。结果是一种单一的语言，它允许用户开发并行应用程序，然后在系统的上下文中对其建模，允许硬件-软件划分和各种其他早期权衡分析。我们相信，这种语言提供了比其他产品更简单、更简洁的语法，可以针对大范围的潜在体系结构，包括异构系统和没有共享内存的系统
{"title":"An Introduction to the Plasma Language","authors":"B. Kahne, Aseem Gupta, Peter Wilson, N. Dutt","doi":"10.1109/MTV.2005.5","DOIUrl":"https://doi.org/10.1109/MTV.2005.5","url":null,"abstract":"The ability to enhance single-thread performance, such as by increasing clock frequency, is reaching a point of diminishing returns: power is becoming a dominating factor and limiting scalability. Adding additional cores is a scalable way to increase performance, but it requires that system designers have a method for developing multithreaded applications. Plasma, (parallel language for system modeling and analysis) is a parallel language for system modeling and multi-threaded application development implemented as a superset of C++. The language extensions are based upon those found in Occam, which is based upon CSP (communicating sequential processes) by C. A. R. Hoare. The goal of the Plasma project is to investigate whether a language with the appropriate constructs might be used to ease the task of developing highly multi-threaded software. In addition, through the inclusion of a discrete event simulation API, we seek to simplify the task of system modeling and increase productivity through clearer representation and increased compile-time checking of the more difficult-to-get-right aspects of systems models (the concurrency). The result is a single language which allows users to develop a parallel application and then to model it within the context of a system, allowing for hardware-software partitioning and various other early tradeoff analyses. We believe that this language offers a simpler and more concise syntax than other offerings and can be targeted at a large range of potential architectures, including heterogeneous systems and those without shared memory","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133516868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Owing to the recent trend of using application-specific instruction-set processors (ASIP), many architecture description languages (ADLs) have been created. They specify architectures or microarchitectures of processors, and automate tasks including circuit implementation, simulation, retargetable compilation and formal verification. This paper first gives an overview of the existing ADLs. This paper argues that for an ADL to be capable of rigorously specifying a processor, it must be based on a solid foundation which we call the architecture model. The existing ADLs feature a wide variety of formal and ad-hoc architecture models which confines the flexibility and analyzability of the ADLs in one way or another. This paper then discusses the operation state machine (OSM) model, the result of our first attempt to create high-level processor models. The model has features balanced flexibility and analyzability for use in architecture space exploration frameworks for ASIPs. This paper also describes the use of the OSM model in the Mescal architecture description language (MADL), an open-source ADL framework that we developed. Lastly, it points out the potential application of formal verification techniques on OSM
{"title":"A Study of Architecture Description Languages from a Model-based Perspective","authors":"W. Qin, S. Malik","doi":"10.1109/MTV.2005.2","DOIUrl":"https://doi.org/10.1109/MTV.2005.2","url":null,"abstract":"Owing to the recent trend of using application-specific instruction-set processors (ASIP), many architecture description languages (ADLs) have been created. They specify architectures or microarchitectures of processors, and automate tasks including circuit implementation, simulation, retargetable compilation and formal verification. This paper first gives an overview of the existing ADLs. This paper argues that for an ADL to be capable of rigorously specifying a processor, it must be based on a solid foundation which we call the architecture model. The existing ADLs feature a wide variety of formal and ad-hoc architecture models which confines the flexibility and analyzability of the ADLs in one way or another. This paper then discusses the operation state machine (OSM) model, the result of our first attempt to create high-level processor models. The model has features balanced flexibility and analyzability for use in architecture space exploration frameworks for ASIPs. This paper also describes the use of the OSM model in the Mescal architecture description language (MADL), an open-source ADL framework that we developed. Lastly, it points out the potential application of formal verification techniques on OSM","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133860404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Quiescent leakage current (Iddq) test has proven very effective for detecting defects that escape other test methods, such as small delay faults or reliability hazards. However, leakage currents in microprocessors, digital signal processors, and graphics processors have risen to the point that these products no longer use Iddq test. Quality must be achieved through other test methods, often at higher development and application cost. We propose to bring Iddq test back to high performance chips by using a practical built-in current sensor (BICS). 180 nm test chip results show that a small sensor can achieve a resolution of 54 muA, which is adequate to detect most small delay defects and reliability hazards
{"title":"Is IDDQ Test of Microprocessors Feasible?","authors":"Bin Xue, D. Walker","doi":"10.1109/MTV.2005.13","DOIUrl":"https://doi.org/10.1109/MTV.2005.13","url":null,"abstract":"Quiescent leakage current (Iddq) test has proven very effective for detecting defects that escape other test methods, such as small delay faults or reliability hazards. However, leakage currents in microprocessors, digital signal processors, and graphics processors have risen to the point that these products no longer use Iddq test. Quality must be achieved through other test methods, often at higher development and application cost. We propose to bring Iddq test back to high performance chips by using a practical built-in current sensor (BICS). 180 nm test chip results show that a small sensor can achieve a resolution of 54 muA, which is adequate to detect most small delay defects and reliability hazards","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115115528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, "properties re-use" and "properties refinement", are described and compared in terms of refinement effort and simulation speed delay
{"title":"On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling","authors":"N. Bombieri, A. Fedeli, F. Fummi","doi":"10.1109/MTV.2005.15","DOIUrl":"https://doi.org/10.1109/MTV.2005.15","url":null,"abstract":"In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, \"properties re-use\" and \"properties refinement\", are described and compared in terms of refinement effort and simulation speed delay","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130882912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
David Berner, Hiren D. Patel, D. Mathaikutty, S. Shukla
The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large percentage of the overall design time. In efforts to alleviate this problem, the authors propose a methodology of using structural reflection to extract structural information from design sources allowing the use of tools such as test bench generators and model viewers to seamlessly employ this extracted information. In this paper the authors present a methodology to automatically extract structural information from already existing SystemC projects and we show how this information can be exploited for system management and validation tasks. The authors illustrate example uses such as visualization, design management tasks, and automated test generation
{"title":"Automated Extraction of Structural Information from SystemC-based IP for Validation","authors":"David Berner, Hiren D. Patel, D. Mathaikutty, S. Shukla","doi":"10.1109/MTV.2005.8","DOIUrl":"https://doi.org/10.1109/MTV.2005.8","url":null,"abstract":"The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large percentage of the overall design time. In efforts to alleviate this problem, the authors propose a methodology of using structural reflection to extract structural information from design sources allowing the use of tools such as test bench generators and model viewers to seamlessly employ this extracted information. In this paper the authors present a methodology to automatically extract structural information from already existing SystemC projects and we show how this information can be exploited for system management and validation tasks. The authors illustrate example uses such as visualization, design management tasks, and automated test generation","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134016252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Bernardi, E. Sanchez, M. Schillaci, M. Reorda, Giovanni Squillero
Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor production is, however, far from ideal. To increase it fault diagnosis is an important means, since it can allow both process characterization and product repair by the usage of backup resources. This paper presents a novel methodology to discriminate faulty modules, rather than gates, in a microprocessor based on the automatic construction of diagnostic software-based test sets. The approach exploits a post-production test set, designed for software-based self-test, and an infrastructure IP to perform the diagnosis. An initial diagnostic test set is built, and then iteratively refined resorting to an evolutionary method. Experimental results are reported in the paper showing the feasibility and effectiveness of the approach for an Intel i8051 processor core
{"title":"Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets","authors":"P. Bernardi, E. Sanchez, M. Schillaci, M. Reorda, Giovanni Squillero","doi":"10.1109/MTV.2005.10","DOIUrl":"https://doi.org/10.1109/MTV.2005.10","url":null,"abstract":"Microprocessor technology is increasingly used for many applications; the large market volumes call for cost containment in the production phase. Process yield for processor production is, however, far from ideal. To increase it fault diagnosis is an important means, since it can allow both process characterization and product repair by the usage of backup resources. This paper presents a novel methodology to discriminate faulty modules, rather than gates, in a microprocessor based on the automatic construction of diagnostic software-based test sets. The approach exploits a post-production test set, designed for software-based self-test, and an infrastructure IP to perform the diagnosis. An initial diagnostic test set is built, and then iteratively refined resorting to an evolutionary method. Experimental results are reported in the paper showing the feasibility and effectiveness of the approach for an Intel i8051 processor core","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132151949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Much current research has focused on employing network-on-chips (NoC's) for communication among numerous cores on large scale SoC's. One side benefit of such designs is the potential to utilize this communication infrastructure with little modification for manufacturing test delivery. In this paper the authors present a test scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower rate test execution at the target cores. To achieve this, test data are interleaved over the network in a time division multiplexed (TDM) approach. Experimental results with the ITC'02 SoC benchmarks are proposed that show substantial test time reduction beyond single speed techniques. Further enhancements are presented that overcome some deficiencies in the simplest approach
{"title":"A TDM Test Scheduling Method for Network-on-Chip Systems","authors":"J. Nolen, R. Mahapatra","doi":"10.1109/MTV.2005.3","DOIUrl":"https://doi.org/10.1109/MTV.2005.3","url":null,"abstract":"Much current research has focused on employing network-on-chips (NoC's) for communication among numerous cores on large scale SoC's. One side benefit of such designs is the potential to utilize this communication infrastructure with little modification for manufacturing test delivery. In this paper the authors present a test scheduling approach for such designs that minimizes test time through high-speed test delivery over the network and lower rate test execution at the target cores. To achieve this, test data are interleaved over the network in a time division multiplexed (TDM) approach. Experimental results with the ITC'02 SoC benchmarks are proposed that show substantial test time reduction beyond single speed techniques. Further enhancements are presented that overcome some deficiencies in the simplest approach","PeriodicalId":179953,"journal":{"name":"2005 Sixth International Workshop on Microprocessor Test and Verification","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2005-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126673628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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