Criteria for static current estimation: how good are they? An approach incorporating IC quality requirements

Abstract

This paper presents a novel approach to estimate the I/sub DDQ/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, our approach proposes the characterization of the faulty circuit quiescent current with respect to an output voltage range characterized by the designer to be defective. This output voltage is defined by the designer in order to meet some desirable quality requirements for the circuit on the design, such as the minimum acceptable noise immunity and maximum time delay. For the design of built-in current sensors, these quality requirements define the minimum current resolution.