DDR2 Memory Controller for Multi-core Systems with AMBA AXI Interface

Abstract

Memories are essential components of any computer system and their performance directly affects the system speed and efficiency. Furthermore, faster, cheaper and higher capacity memories are a demand that is increasing each day however this demand comes at the cost of complexity and other drawbacks. This paper introduces a multi-port DDR2 SDRAM controller that supports an AMBA AXI interface at each port. The design is responsible for memory initialization and automatic generation of refresh sequences. Round Robin arbitration algorithm is adopted in the design. The proposed design is successfully synthesized on xc7z020clg484-l (zedboard) with maximum operating frequency of 212 MHz which improves the design speed by around 30%. The area of the design has been also improved by around 40%.