A bounded carry inspection adder for fast parallel arithmetic

Abstract

This paper suggests a new mechanism for parallel, high-speed arithmetic for digital computers. It is based on a bounded carry inspection adder (BCIA) that operates on ternary coded data words. The recoding circuitry is of the type currently in use in computers that perform high-speed multiplication by the modified short cut (MSC) technique of shifting over ones and zeros. The uniqueness of the BCIA lies in the application of this recording to addition, and to an even greater speed-up of the multiplication technique that fostered it. In the process of multiplication, repeated additions/subtractions are required. The BCIA speeds up the process by providing an addition technique that yields the sum in parallel in one step through the elimination (bounding) of carry propagation.