{"title":"Design and implementation of floating point multiplier based on Vedic Multiplication Technique","authors":"Aniruddha Kanhe, S. K. Das, Ankit Kumar Singh","doi":"10.1109/ICCICT.2012.6398204","DOIUrl":null,"url":null,"abstract":"In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.","PeriodicalId":319467,"journal":{"name":"2012 International Conference on Communication, Information & Computing Technology (ICCICT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"45","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Conference on Communication, Information & Computing Technology (ICCICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCICT.2012.6398204","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 45
Abstract
In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyakbhyam sutra is used for the multiplication of Mantissa. The underflow and over flow cases are handled. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The multiplier is implemented in VHDL and Virtex-5 FPGA is used.
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