Predictive LBIST model and partial ATPG for seed extraction

Abstract

Integrated circuits used in critical and high reliability applications have often strict test requirements including high test coverage and limited test time. Achieving a high test coverage using built-in self-test (BIST) has proven difficult. Methods such as test point insertion or deterministic BIST can provide high test coverage but introduce significant area overhead and design effort. In this paper, we propose a computational algorithm that uses a linear XOR model of the logic BIST (LBIST) structure and fault partitioning to extract seeds for partial ATPG patterns. Partial ATPG patterns are used to decrease the complexity of the algorithm when solving linear XOR equations to generate deterministic seeds. The extracted seeds are stored in a nonvolatile memory on- or off-chip. Results show that for most designs, patterns generated from the extracted ATPG seeds are significantly more effective in detecting faults and can achieve higher test coverage than LBIST.