{"title":"Incremental netlist compilation for IKOS hardware logic simulator","authors":"K. Wang, J. Chen","doi":"10.1109/ASIC.1989.123223","DOIUrl":null,"url":null,"abstract":"Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be reproduced and can be loaded to the simulator for the times of occurrences by adjusting for the base offsets.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"271 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1989.123223","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Incremental compilation is desirable to avoid recompiling a large network when only a few modules are modified. An algorithm that partitions a network in a hierarchical manner is described. The linker links together separately compiled or linked modules to generate machine codes for the IKOS hardware simulator. The machine codes generated for the duplicate subnetworks (or logic blocks) need not be reproduced and can be loaded to the simulator for the times of occurrences by adjusting for the base offsets.<>
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